asynchronous connection - translation to English
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  3. asynchronous connection

asynchronous connection - translation to English

SYSTEM HAVING NO GLOBAL CLOCK, INSTEAD OPERATING UNDER DISTRIBUTED CONTROL
Asynchronous Systems; Asynchronous systems

asynchronous connection      

общая лексика

асинхронная связь [передача]

режим передачи данных, при котором временной интервал между передаваемыми символами может изменяться (в отличие от режима синхронной связи). Чтобы отличить поступающие данные от шума в линии, используются специальные сигналы: стартовый и стоповый биты

Смотрите также

asynchronous data transmission

clockless         
  • Illustration of two and four-phase handshakes. Top: A sender and a receiver are communicating with simple request and acknowledge signals. The sender drives the request line, and the receiver drives the acknowledge line. Middle: Timing diagram of two, two-phase communications. Bottom: Timing diagram of one, four-phase communication.
  • A 4-phase, bundled-data communication. Top: A sender and receiver are connected by data lines, a request line, and an acknowledge line. Bottom: Timing diagram of a bundled data communication. When the request line is low, the data is to be considered invalid and liable to change at any time.
  • Diagram of dual rail and 1-of-4 communications. Top: A sender and receiver are connected by data lines and an acknowledge line. Middle: Timing diagram of the sender communicating the values 0, 1, 2, and then 3 to the receiver with the 1-of-4 encoding. Bottom: Timing diagram of the sender communicating the same values to the receiver with the dual-rail encoding. For this particular data size, the dual rail encoding is the same as a 2x1-of-2 encoding.
DIGITAL CIRCUIT WITHOUT CLOCK CYCLES
Asynchronous logic; Asynchronous vlsi; Clockless Logic; Clockless computing; Clockless; Clockless processor; Asynchronous Processor; Clockless logic; NULL convention logic; Vennjunction; Clockless CPU; Asynchronous CPU; Four-phase handshake; Asynchronous design; Asynchronous computer

общая лексика

асинхронные схемы

несинхронизированные схемы

нетактированные схемы

buffer plate         
  • A preserved corridor tender. The passageway runs along the side closest to the camera; the top of the passageway may be seen at the rear
  • This British locomotive has a centre buffing plate similar to that fitted to the lower portion of a Pullman-type gangway connection.
  • A GWR coach fitted with a British Standard gangway connection of the "suspended" type
  • Internal view of gangways between a [[British Rail Class 153]] and a [[British Rail Class 158]]. Notice the doors on the sides, which prevent passengers from accessing the cabs of either unit. When the gangway is not in use, they lock outwards to block off the entire cab/gangway compartment.
  • post office stowage tender]] with offset gangway connection
  • LNER Class A1 4-6-2]] with corridor tender. Circular window of passageway at upper right of tender rear.
  • View along full length of a [[Toronto Rocket]], [[folding seat]]s at the right
FLEXIBLE CONNECTOR FITTED TO THE END OF A RAILWAY COACH, ENABLING PASSENGERS TO MOVE FROM ONE COACH TO ANOTHER
Corridor (rail vehicle); Corridor tender; Corridor connection; Buffer plate; Corridor connector; Open gangway; Open-gangway

общая лексика

буферная панель

Definition

asynchronous logic
<architecture> A data-driven circuit design technique where, instead of the components sharing a common clock and exchanging data on clock edges, data is passed on as soon as it is available. This removes the need to distribute a common clock signal throughout the circuit with acceptable {clock skew}. It also helps to reduce power dissipation in CMOS circuits because gates only switch when they are doing useful work rather than on every clock edge. There are many kinds of asynchronous logic. Data signals may use either "dual rail encoding" or "data bundling". Each dual rail encoded Boolean is implemented as two wires. This allows the value and the timing information to be communicated for each data bit. Bundled data has one wire for each data bit and another for timing. Level sensitive circuits typically represent a logic one by a high voltage and a logic zero by a low voltage whereas transition signalling uses a change in the signal level to convey information. A speed independent design is tolerant to variations in gate speeds but not to propagation delays in wires; a delay insensitive circuit is tolerant to variations in wire delays as well. The purest form of circuit is delay-insensitive and uses dual-rail encoding with transition signalling. A transition on one wire indicates the arrival of a zero, a transition on the other the arrival of a one. The levels on the wires are of no significance. Such an approach enables the design of fully delay-insensitive circuits and automatic layout as the delays introduced by the layout compiler can't affect the functionality (only the performance). Level sensitive designs can use simpler, stateless logic gates but require a "return to zero" phase in each transition. http://cs.man.ac.uk/amulet/async/. (1995-01-18)
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Wikipedia

Asynchronous system

The primary focus of this article is asynchronous control in digital electronic systems. In a synchronous system, operations (instructions, calculations, logic, etc.) are coordinated by one, or more, centralized clock signals. An asynchronous system, in contrast, has no global clock. Asynchronous systems do not depend on strict arrival times of signals or messages for reliable operation. Coordination is achieved using event-driven architecture triggered by network packet arrival, changes (transitions) of signals, handshake protocols, and other methods.

https://en.wikipedia.org/wiki/Asynchronous system
What is the Russian for asynchronous connection? Translation of &#39asynchronous connection&#39 to R
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